Components for Building Computers From Scratch/FSB
I know a lot of PCs today did away with the Northbridge and the CPU has the Northbridge on it.
But the older PCs had the CPU and Memory and AGP Slot connected to the Northbridge? And the speed from the CPU to the Memory and the AGP Slot was the FSB?
Conventional modern CPUs have a lot of things integrated into them, depending on the specific chip this can be as simple as a memory controller (like on the Athlon64) or can include PCI Express connectivity, integrated graphics, integrated audio DSPs, and so on (like on the AMD A10). The CPU will also connect to an ICH (I/O Controller Hub) via QPI (Intel) or HTT (AMD) to provide additional I/O for the system (such as PCI Express lanes, disk connectivity, USB, and PCI (if available)).
With older systems, say a Pentium 4, the CPU connects to a device known as an MCH (Memory Controller Hub) or "Northbridge" via FSB, and the MCH acts as a memory controller (it then "talks" to the memory at whatever the best common speed is), as well as providing a bridge to the I/O controller hub (ICH or "Southbridge") and connection to the AGP slot (if available). The MCH->ICH connection is proprietary to whoever is providing those chips (and often to a specific generation of chips) and generally provides fairly high bandwidth because of the amount of I/O the ICH has to handle. The various expansion slots and other connectors (SATA, PATA, etc) connect back to the system at whatever their rated bandwidth is, and this is handled by the MCH/ICH pair depending on the devices involved.
Here's some block diagrams that illustrate real-world products:
And devices that don't rely on a MCH:
The primary advantages to modern designs are better realized in SMP systems, where multiple processors are involved. Using something like HTT or QPI allows the processors to both communicate directly with one another and address memory directly. For example:
Contrasted to older designs that required much more complex MCH devices to connect two or more CPUs, and relied on the CPUs sharing memory bandwidth and FSB bandwidth.