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Expert: cleggsan - 10/31/2009
Question
Hi
I am a 4th year student doing a project in encoding and encryption. The project involves the hardware design of various encoding and encryption techniques and this design is to be carried out using VHDL with FPGA technology.
My problem is in compiling the code for a 'Hamming' generator. I am using a program called Quartus(Altera). I have realised that I can use the lpm megafunctions given in the software to help, in particular the lpm xor and the lpm shift register. However I am unsure as to how this shift register will work.
Firstly is the actual implementation of the register incorporated in the component declaration?
Secondly do I need to cascade the registers for 4 bit parity, i.e. an 8 to 12 bit register? The placement of the parity bits in the string using a shift register seems to me to be quite difficult.
Should you have any experience with this software and it's functions any help would be much appreciated.
Kind Regards,
Maria
Answer
I found some discussion about that in this paper:
http://www.ti.uni-bielefeld.de/downloads/publications/diploma_theses/da03_mgrieg...
But, honestly I don't know the answer to it. I am going to consult with my digital expert and see if I can find more from him. Give me a day or two to get further information.
Hope this helps.
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