This problem is giving me a huge headache. I've drawn out the series but still confusing.
Your engineering team is tasked with designing a single stage (LC) tunable filter interface that will provide a voltage gain of 12- at a tuned frequency of 1.2 MHz.The signal that you are processing requires a bandwidth of 10KHz to maintain signal fidelity. The stage feeding your interface, provides a signal voltage of 10mv ( cenrered at 1.2 MHz), and exhibits an output impedance ( Thevenin Equivalent) of value R1 ( with a phase angle of 0 degrees). You need to maximize the allowable value of R1 in your design. Once you have calculated the values for C, L, Vc, R1( show all necessary intermediate calculations sketch the approximate frequency response of the output voltage versus frequency.
I've already completed the sketch. Thank you
This is a bandwidth issue. Bandwidth is calculated from the Q or Quality factor of the circuit. It needs a bandwidth of 10Khz. The bandwidth of an LC tuned circuit is fixed by the resistor used in series (for a series tuned circuit) or in parallel (for a parallel tuned circuit).
The Q of the tuned circuit and how to adjust the Q is shown in the following examples:
Hope this helps.